Engineering brief
When AI Writes Your Chip, Who Checks the Work?
At a glance
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An engineer used AI agents to build a 500k-line Verilog simulator in 43 days, sidestepping $10k-per-seat EDA licenses. In hardware, passing 70% of tests usually means the design is completely wrong, creating a verification gap that cannot be closed by test coverage alone.
AI is breaking the EDA cost barrier, but the verification crisis it creates could introduce billion-dollar bugs.
Summary
Thomas Ahle built an open-source Verilog simulator using AI agents, producing 500,000+ lines in 43 days. Proprietary EDA tools cost $10k per seat per core, stifling innovation. AI-generated toolchains could cut costs and democratize chip design, but they introduce a critical verification problem.
Passing 70–80% of tests in AI-generated code often means nothing—Ahle notes many benchmarked programs that appear partially correct are completely wrong. In hardware, where bugs cost hundreds of millions, this gap is existential. Orthogonal teams and formal methods are standard, but AI agents blur those lines, creating understanding debt that compounds.
Thermodynamic computing—a chip that harnesses noise as computation—represents a longer-term bet for probabilistic workloads like Bayesian inference. While a first silicon prototype exists, it remains narrow and early-stage. The real near-term impact lies in AI’s ability to generate and verify RTL, potentially collapsing the iterative design-verify loop if trust can be established.
Engineering leaders should watch the shift from deterministic verification to managing stochastic trust in AI outputs. The economic incentive to replace expensive tooling is huge, but without new governance and validation strategies, teams risk building on foundations they don't understand and cannot debug.
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